Method and system for partial-scan testing of integrated ciruits

ABSTRACT

A method and system for partial scan testing of integrated circuits is disclosed. The invention includes determining at least one failed functional block during testing of the integrated circuit. The failed functional block is then logically isolated from the remaining non-failing functional blocks. Scan testing of the remainder of the non-failing functional blocks then occurs to determine the integrity of the remainder of the integrated circuit. The data coming out of the failing functional block is not allowed into the other functional blocks as input data. The invention allows the integrated circuit to be used and sold at a reduced functionality for applications not requiring the failed functional block(s).

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to the testing ofintegrated circuits. More particularly, the invention relates to scantesting of integrated circuits to determine failed functional blocks andpartially scan testing the integrated circuit without the failedfunctional blocks such that the integrated circuit may be tested andsold at a reduced functionality.

[0002] Integrated circuitry on a chip is commonly tested. Scan testingis a common way to test integrated circuits by serially shifting testdata into an integrated circuit, and then observing the output of theserial data. This method is very effective to determine whether anentire integrated circuit is functioning properly, and may be packagedand sold. The production chips of an integrated circuit to be sold arechecked for manufacturing flaws before being furnished to a customer.Testing may also include applying a test program to the circuitry todetermine if the logic on the chip responds as desired to variouselectrical inputs.

[0003] Due to processing improvements, it is possible to include anentire computer system on a chip. What was once a number of complexdedicated chips on a motherboard is now a number of complex blocks in anintegrated circuit. The number of transistors in the integrated circuitmay number in the tens of millions, or even more. The failure of asingle transistor within one of these complex blocks will cause anintegrated circuit to fail scan testing. As a result, the chip will bescrapped, resulting in a lower yield of usable chips, as well as higherproduction costs.

[0004] In scan testing, each flip-flop in a design to be tested has twoinput paths, one a functional path, and the other a test path. Eachflip-flop in the integrated circuit (IC) is connected serially throughthe test path. That is, one flip-flop output is tied to the test inputof another single flip-flop. A test program may include one or more scanpatterns to be applied to the block of the circuit to be tested. First,data is scanned in through the serial test inputs to initialize all theflip-flops in the design. Then the functional input is used to capturedata from the cone of logic in the parallel path. This loads eachflip-flop with a new value, which is then shifted serially through thetest input again. The process continues for many cycles, and serial datais shifted in through the test inputs, and then captured through thefunctional outputs. After running many cycles, test coverage increasesas many different patterns will be run through the cone of logic in thefunctional path to each flip-flop. The serial scan chains are observedon the integrated circuit outputs, and if a serial pattern matches theexpected result, then the IC is deemed good. A typical test sequence ina scan pattern consists of a scan-in operation, a set of input stimulus,and a scan-out operation. Desired values are loaded into the scanflip-flops. During the implementation of a scan, a circuit design istested as one entity, and the design flip-flops are interconnected intoa single, long shift register, or in other words a scan chain. Valuesare loaded and/or extracted from the scan flip-flops by seriallyshifting in and out one bit per clock cycle.

[0005]FIG. 1 discloses a block diagram illustrating a prior artfunctional block arrangement. This arrangement illustrates a typicalhigh-level integration design in which there are a number of majorfunctional blocks, in this case block A, block B and block C. In thisarrangement, the functional mode, blocks B and C both depend on block Ato function. In integrated circuit 10, the output of block A goes to theinput of block B via line 12A and conversely the output from block Bgoes to the input of block A via line 12B. Similarly, the output ofblock A goes to block C via line 14A and the output of block C goes toblock A via line 14B. In each case, each of the functional blocks A, Band C send and receive data via their respective bus line 16A, 16B and16C. In this arrangement, blocks B and C both depend on block A tofunction. However, blocks B and C do not depend on each other tofunction. Therefore, in such an arrangement, if a failure is detectedduring testing of block A, the entire integrated circuit 10 must bescrapped because there is no ability to salvage the functionality of theremaining blocks. This is due to the fact that block A affects bothblock B and block C. The inability to prevent information coming out ofblock A (which is unreliable) from affecting the logic of blocks B and Cmakes any properly functioning blocks also unreliable. An exampleillustrating this concept would be an integrated circuit design whereblock A is a bus interface to a microprocessor, block B is a fire wireinterface, and block C is a USB interface. In short, there is no way inthe conventional design to bypass a failed functional block fromcorrupting valid functional block logic.

[0006] The problem with this technique in current applications is thatif there is a failure in one section of the integrated circuit (IC) thefailing section cannot be prevented from affecting the logic in the restof the IC. Consequently, it is not possible to prove that the rest ofthe IC is good silicon, and therefore producing valid logic. Therecurrently are techniques that use partial scan testing of individualfunctional blocks, but these techniques do not adequately test theinteraction between the functional blocks, because the failure of oneblock will corrupt the logic of any associated blocks. Therefore, thetesting of functional blocks individually is not useful since theycannot be tested in logical isolation. It is desired to provide a way toisolate an entire functional block from the rest of the integratedcircuit and partially test the integrated circuit even when portions ofthe IC have failed.

SUMMARY OF THE INVENTION

[0007] The present invention solves the above-identified problems andallows any number of functional blocks within the IC to be isolated, andtherefore logically removed from scan testing, allowing the rest of theIC to be tested normally. By isolating a failing block and continuingtesting, the entire IC does not have to be scrapped. It could bepackaged and sold at a reduced cost without the failing functionality.This would then increase the yield of the IC batch, and lower the costsof producing the IC. For example, if a system on a chip IC were to failduring full scan testing, and the failure was isolated down to a singlefunctional block, for example an interface, the chip could be packagedand resold into markets that do not require the particular interface.

[0008] In accordance with one aspect of the invention, the method ofpartial scan testing an integrated circuit is disclosed. The methodincludes initially scan testing an integrated circuit, and thendetermining from the scan testing at least one failed functional blockin a group of non-failing functional blocks. The method includeslogically isolating an output of the at least one failed functionalblock from the group of non-failing functional blocks. After theisolating, the method includes scan testing the group of non-failingfunctional blocks of the integrated circuit.

[0009] In another aspect of the invention, a method of testing anintegrated circuit includes the steps of identifying at least one failedlogic section of the integrated circuit during scan testing. The failedlogic section is then logically isolated from a remainder of theintegrated circuit. The method includes testing the integrated circuitwithout utilizing the failed logic section to permit operation of theintegrated circuit at a reduced functionality.

[0010] In yet another aspect of the invention, an integrated circuit isdisclosed and includes at least one functional block that has failed ascan test and at least one non-failing functional block logicallyconnected to the failing functional block. The invention includeslogical circuitry connected to the at least one failed functional blockand the at least one non-failing functional block to isolate the failingfunctional block from the non-failing functional block during testingand operation of the integrated circuit.

[0011] Accordingly, it is the object of the present invention to allowthe testing and operation of an integrated circuit at a reducedfunctionality by isolating failed functional sections from non-failingfunctional sections.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings illustrate the best mode presently contemplated forcarrying out the invention.

[0013] In the drawings:

[0014]FIG. 1 is a block diagram of a prior art functional blockarrangement.

[0015]FIG. 2 is a schematic illustrating the integrated circuit inaccordance with the present invention.

[0016]FIG. 3 shows a portion of the integrated circuit of FIG. 2.

[0017]FIG. 4 is a flowchart illustrating the method in accordance withone aspect of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018] Referring to FIG. 2, an example of a series of functional blocksin accordance with the present invention is illustrated. Although threesections identified generally by sections 100, 102 and 104 are shown,such sections will be repeated along the integrated circuit and would berepeated in a chain or array. The number of sections is limited only bythe number of functionalities in the integrated circuit. Each section100, 102 and 104 includes a functional block A, B and C, respectively.Each functional block A, B and C is a section of logic that performs afunction that is able to be partitioned from the remainder of theintegrated circuit. Functional blocks A, B and C may in themselves becomplex circuits that together form a single function.

[0019] Referring to FIG. 3, section 102 of FIG. 2 is shown. It is to beunderstood that the functions, electrical connections and relationshipsbetween the functional block and the testing logic are the same forsections 100 and 104, as will be explained with respect to section 102.

[0020] Functional block B includes input 106 and output 108, multiplexer110 or other selected connector. Multiplexer 110, in this case atwo-to-one multiplexer, has a functional input 112 which is tied in fromthe previous functional block (functional block A of FIG. 2) andisolating input 114 and multiplexer output 116, which is connected tothe input 106 of functional block B. Multiplexer 110 also includes anisolating select input 118 which is used to select between functionalinput 112 and isolating input 114.

[0021] As is known in the art, scan testing is often used to determinethe correct functioning of a functional block of logic within anintegrated circuit. To that end, functional block B includes a serialscan line output 120. During normal scan mode, data is shifted in andout of testing flip-flop 122 in a serial fashion. The serial datashifted into functional block B input 106 is observed coming out ofserial scan output line 120 and into flip-flop 122. Flip-flop 122 may beany type of register, and includes clock signal 124 and data input 126from the functional block B. Serial scan line 120 is a path for serialdata during test mode, but flip-flop 122 does not contribute to theoverall functionality outside the testing of the chip.

[0022] In operation, during scan testing of functional blocks A, B andC, if it was determined that functional block A was producing invaliddata, it would be necessary to isolate the data stream from enteringfunctional block B. Therefore, isolation select line 118 would beenabled in order to select line 114 entering multiplexer 110, ratherthan functional input 112 from functional block A in this case. Isolatedinput 114 represents output from test flip-flop 122 which stores output108 from functional block B. In essence, the output from functionalblock B is rerouted as its own input, thereby isolating functional blockA from the remainder of the logic circuit. Because the output frominvalid functional block A 112 is not selected, it is not an issue todetermine the status of that data line, since it is not selected bymultiplexer 110. It is known, however, that functional block B has anoutput that is valid during testing and therefore that output isrerouted via isolating input 114 in order to isolate functional block A.

[0023] In a similar manner, if during scan testing it was determinedthat functional block B's output was invalid, functional block output108 would not be selected to enter the next multiplexer associated withthe next functional block (for example, functional block C of FIG. 2).In this manner, each functional block is capable of isolating theprevious functional block output from the remainder of the integratedcircuit to enable scan testing of the valid functional blocks in theintegrated circuit.

[0024] Referring to FIG. 4, a flowchart illustrates the methodologyassociated with the present invention. In block 128, testing commencesof the integrated circuit. It is preferred in the present invention touse scan testing as the testing method. This testing is of allfunctional blocks in the integrated circuit. During this full testing,it is determined as shown by block 130 what the functional block testoutput is of each functional block based upon the input scan test data.In the beginning of testing, this will entail determining the validityof each functional block, whereas later in the procedure it is onlynecessary to determine the test output of valid functional blocks. Adetermination is made at 132 whether the output of the functional blocksof interest are valid. This is determined in a known manner based uponcomparison of the scanned in serial data and the output of each of thefunctional blocks as shifted through their respective flip-flops viatheir serial scan chains. If the output is valid 134, a determination ismade at 136 whether testing is complete. If yes, 138 testing iscompleted and the procedure is ended 140. If not, 142 testing continuesas shown in block 144 and again functional block test outputs aredetermined. If that decision 132 output of any functional block is notvalid, at block 148 that invalid functional block is identified. As aresult of the identification of an invalid functional block, theisolating select line is enabled for the multiplexer receiving theoutput of that invalid functional block. This in effect blocks theoutput of the invalid functional block from corrupting the logic of theremaining functional blocks. The scan test then continues without theinvalid functional block data entering any further functional blocks. Apartial scan test is created because the output from the invalidfunctional blocks is not utilized. The partial scan test continues in atypical fashion to determine whether the remainder functional blocks areoutputting valid data based upon the test input data at 132. Thisprocedure continues until all of the output data is valid, testing iscomplete and the invalid functional blocks are identified. Thenow-tested IC may be used at a reduced functionality without the invalidfunctional blocks that failed scan testing.

[0025] In such a manner, it can then be determined whether theintegrated circuit can be sold without the functioning of the invalidfunctional blocks. The reduced functionality integrated circuit can thenbe utilized where it would normally have been scrapped. However, in thisinstance, the invalid functional blocks had been identified andseparated out from the remainder of the integrated circuit.

[0026] The present invention has been described in terms of thepreferred embodiment, and it is recognized that equivalents,alternatives, and modifications, aside from those expressly stated, arepossible and within the scope of the appending claims.

I claim:
 1. A method of partial scan testing an integrated circuitcomprising the steps of: initially scan testing an integrated circuit;determining from the scan testing at least one failed functional blockand a group of non-failing functional blocks of the integrated circuit;logically isolating an output of the at least one failed functionalblock from the group of non-failing functional blocks; scan testing thegroup of non-failing functional blocks of the integrated circuit afterthe isolating step.
 2. A method of partial scan testing an integratedcircuit comprising the steps of: scan testing an integrated circuit;determining at least one failed logical section and a group ofnon-failing logical sections; logically isolating the at least onefailed logical section from the group of non-failing logical sections;scan testing the group of non-failing logical sections of the integratedcircuit.
 3. The method of claim 2 wherein the scan testing of the groupof non-failing logical sections occurs after the step of logicallyisolating the at least one failed logical section from the group ofnon-failing logical sections.
 4. The method of claim 2 wherein thelogically isolating step is performed by a multiplexer.
 5. The method ofclaim 2 wherein the failed logical section constitutes a functionalblock of the integrated circuit.
 6. The method of claim 2 furthercomprising the step of determining, as a result of scan testing thegroup of non-failing logical sections, that the integrated circuit maybe utilized at a reduced functionality.
 7. A method of isolating afunctional logic block in an integrated circuit for partial scantesting; providing at least one functional block having a functionalblock input and a functional block output; connecting a register havingat least one register input connected to the functional block output anda register output; providing a selective connector having an isolatinginput, an isolating select input, a functional input and a selectiveconnector output; connecting the register output to the selectiveconnector isolating input; connecting the selective connector output tothe functional input; enabling the isolating select input of theselective connector such that the register output is fed into thefunctional block to logically isolate the functional block from theintegrated circuit.
 8. The method of claim 7 wherein the register is aflip-flop.
 9. The method of claim 7 wherein the selective connector is amultiplexer.
 10. A method of utilizing an integrated circuit at areduced functionality comprising of steps of: providing an integratedcircuit having a plurality of functionalities defined by a plurality offunctional blocks within the integrated circuit; determining duringtesting a failure of at least one of the functional blocks; isolatingelectronically the at least one failed functional blocks from aremainder of the functional blocks; and testing the integrated circuitwithout the functionality of at least one failed functional blockaffecting the functionality of a remainder of the plurality offunctional blocks.
 11. The method of claim 10 wherein the testing isscan testing of the integrated circuit.
 12. A method of providing areduced functionality integrated circuit comprising the step ofproviding an integrated circuit having a plurality of functional blocksand at least one failed functional block wherein the integrated circuitmay operate at the reduced functionality without the failed functionalblock contaminating data of the plurality of functional blocks.
 13. Amethod of testing an integrated circuit comprising the steps of:identifying at least one failed logic section of the integrated circuitduring scan testing; logically isolating the failed logic section from aremainder of the integrated circuit; and testing the integrated circuitwithout utilizing the failed logic section to pen-it operation of theintegrated circuit at a reduced functionality.
 14. A method of isolatinga logic section of an integrated circuit comprising the steps of:providing a first functional block connected to a second functionalblock via a selective connector having an isolating select line;providing a register having an output and connecting the register outputto an input of the selective connector; connecting an output of thesecond functional block to an input of the register; connecting theregister output to an isolating input of the selective connector; andenabling the isolating select line such that the selective connectorselects the isolating input and does not select the first functionalblock.
 15. The method of claim 14 wherein first functional block isdetermined to be a failed logic section.
 16. A method of isolating anintegrated circuit for testing comprising the steps of: inputting afirst input from a failed logic section into a 2×1 multiplexer;inputting a second input from a non-failed logic section into themultiplexer; providing an isolating select line to the multiplexer;enabling the isolating select line to select the second input from thenon-failed logic section and isolate the failed logic section from thenon-failed logic section; and testing the non-failed logic section ofthe integrated circuit.
 17. The method of testing an integrated circuitcomprising the steps of: conducting scan testing of an integratedcircuit; determining at least one valid functional block and at leastone invalid functional block; isolating an output from the invalidfunctional block such that the output is not introduced to any of thevalid functional blocks; continuing scan testing of the valid functionalblocks.
 18. The method of claim 17 wherein the isolating step includesutilizing the output of one of the valid functional blocks rather thanthe output of the invalid functional block.
 19. The method of operatingan integrated circuit having a plurality of logic sections comprisingthe step of: operating an integrated circuit at a reduced functionalityby bypassing at least one of the functional logic units such that thereduced functionality of the integrated circuit does not includeutilization of the bypassed functional logical unit.
 20. An integratedcircuit comprising: a logic circuit having a plurality of functionalblocks each having a functional block input and a functional blockoutput; a multiplexer logically connected between a pair of theplurality of functional blocks, each multiplexer having an isolatinginput, an isolating select input, an output connected to one of theplurality of functional blocks and an input connected to another of theplurality of functional blocks; a register having a register inputconnected to one of the functional block outputs and a register outputconnected to the isolating input of the multiplexer; wherein each of thefunctional blocks is capable of being logically isolated from the logiccircuit.
 21. An integrated circuit comprising: a plurality of functionalblocks; and logical circuitry connected to at least one of thefunctional blocks to permit an output of each of the functional blocksto be selectively logically isolated from a remainder of the pluralityof functional blocks.
 22. An integrated circuit for partial scan testingcomprising; a plurality of functional blocks; a testing multiplexerhaving an output electrically connected to each of the functional blocksand an input electrically connected to another of the functional blocks;a testing flip-flop having an input electrically connected to each ofthe functional blocks and an output electrically connected to anisolating input of the multiplexer; wherein the multiplexer includes anisolation select line that causes the multiplexer to select theisolating input connected to the output of the flip-flop and does notselect the input from any of the other functional blocks when enabled.23. An integrated circuit comprising: at least one functional block thathas failed a scan test; at least one non-failing functional blocklogically connected to the failing functional block; logical circuitryconnected to the at least one failed functional block and the at leastone non-failing functional block to isolate the failing functional blockfrom the non-failing functional block during testing and operation ofthe integrated circuit.
 24. The integrated circuit of claim 23 whereinthe logical circuitry prevents an output signal of the at least onefailed functional block from being input into the non-failing functionalblocks.
 25. The integrated circuit of claim 23 wherein the at least onefailed functional block is a functional logic section and wherein thefailed logic section is determined during scan testing of the integratedcircuit.
 26. The integrated circuit of claim 23 wherein the logicalcircuitry includes a multiplexer to logically isolate an output of thefailed functional block from the non-failing functional blocks.